Two phase clock counter circuits are utilized extensively in integrated circuit applications. Known counter circuits generally have problems that make them difficult to implement in many high speed counting applications.
A first previously known type of counter is referred to as a carry-ripple counter. This counter typically comprises serially coupled T type flip-flop registers in which each register provides one digit of the counter. Accordingly, the counter generates the counts in a serial manner. The problem with this type of counter is that it is very slow.
For those situations where the counter must operate at high speeds serial coupling represents a significant disadvantage. In such an arrangement the clock input of one T flip-flop is coupled to the output of the previous T flip-flop. In so doing, a signal is propagated through all of the gates in the series string to provide the sequential counting. This propagation represents a large number of gate delays when several gates are utilized to provide the digit outputs for the counter. Gate delays represent the additional time required for the counter to perform its function. Hence, this type of counter, although effective for many applications, is undesirable in very high speed applications.
FIG. 1 depicts, in block diagram form, a typical "carry ripple " counter 10. This counter 10 comprises flip-flops 12 and 24 coupled in a serial counter configuration. In this circuit, an input signal is provided to the clock input of T flip-flop 12 via lin 14. The data termina 20 of T flip-flop 12 is coupled to the complement Q terminal 22 visa line 18. The complement Q terminal 22 is in turn coupled to the clock terminal 26 of the flip-flop 24 via line 16. The data input 28 of flip-flop 24 is coupled to the complement Q terminal of the flip-flop 24 via line 20.
In this embodiment, the Q output terminal 32 of flip-flop 12 provides the "ones" digit of the counter 10 in binary nomenclature. The Q output terminal 34 of flip-flop 24 provides the "twos" digit of counter 10 in binary nomenclauture. Although in this embodiment only two flip-flops are shown coupled in series, it should be understood by one of ordinary skill in the art that any number of these flip-flops can be used depending upon the required application.
Although this type of counter works effectively for its intended purpose, it is not suitable for high speed applications. In this type of carry ripple counter 10, there are a significant number of gate delays that cause this type of counter to be extremely slow when using a number of flip-flops. Therefore, it is necessary to provide a counter that overcomes the above-mentioned speed problems.
An alternative to the above mentioned counter is a parallel counter that includes carry look-ahead logic. This counter has the advantage of providing the counts to the output in parallel thereby significantly increasing the speed of operation. Typically this type of counter comprises an adder that receives the signals representing the counts in a parallel manner and a register for receiving and storing those parallel bits from the adder. Coupled to the adder is logic circuitry for providing the carry-bit to the adder.
A parallel counter is shown in FIG. 2. This counter 60 comprises an adder 62 and register 64. In counter 60, the adder 62 includes carry lookahead logic (not shown) and provides the counts to the register 64 in parallel. Register 64 then outputs those bits via line 68. Although counter 60 is much faster than the counter 10 of FIG. 1, it requires complex circuitry in a practical implementation. The problems with this type of counter are clarified with reference to FIG. 3.
FIG. 3 is a more detailed block diagram of a counter 60 shown in FIG. 2. Shown are adders 70, 74, and 78. Each of these adders receive 4 bits of information value. Register 72 is coupled to adder 70 via line 80. Register 76 is coupled to adder 74 via line 82. Register 84 is coupled to adder 78 via line 84. Carry logic circuit 92 is coupled to the input of adder 70 via line 86. Carry logic cicuit 94 is coupled to input of adder 74 via line 96 and is also coupled to carry logic circuit 92. Carry logic circuit 100 is coupled to the input of adder 78 and to the carry logic circuits 92 and 94. In such an embodiment, register 72 outputs bits 0-3, register 76 outputs bits 4-7, and register 84 outputs bits 8-11, all in parallel.
This type of counter is much faster than counter 10 of FIG. 1, but as is seen by the block diagram representation shown in FIG. 3, it is a more complex circuit system than that of FIG. 1.
A parallel counter of this type is significantly faster than a comparable carry ripple counter as described above, however this counter has the disadvantage of requiring additional logic circuitry to provide the carry look-ahead function. In large counter arrays, the speed of the counter is limited by how fast the carry-bit can be computed by the carry-logic. It is known that there is a tradeoff in carry-bit design between the amount of complexity that is required for the carry-bit logic and the amount of die size taken up by that logic. Hence, it is desirable to provide a circuit which does not require this tradeoff. It is also necessary to provide a circuit which can be easily adapted to integrated circuit techniques and processes.
An additional problem with this type of logic circuitry is that it adds significant complexity to the counter, in addition to adding to the overall die size of the counter. These two disadvantages represent a significant cost disadvantage. Firstly, the additional logic circuitry can add expense to the manufacture and production of the integrated circuit that may cause the circuit to be unfeasible from a commercial standpoint.
Secondly, the use of this additional circuitry will significantly increase the power consumption of the circuit. This additional power consumption represent a significant disadvantage in integrated circuit applications and should be avoided whenever possible.
Finally this type of counter has the disadvantage of using an increased amount of die area on the integrated circuit due to the logic circuitry necessary for the carry bit. As is well known, die area is at a premium in integrated circuits. All of the above mentioned disadvantages substantially minimize the advantages of the parallel counter.
Hence, what is needed is a counter which has the advantage of being applicable to high speed applications but none of the disadvantages associated with known high speed counters. In addition, the counter must be capable of practical implementation in integrated circuit technology. Accordingly what is provided in the present invention is a high speed counter that overcomes the above mentioned problems.